Imaging devices, including charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) imagers, are commonly used in photo-imaging applications.
A CMOS imager circuit includes a focal plane array of pixels, each of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge a portion of the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel cell may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel cell for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
With reference to FIGS. 1 and 2, which respectively illustrate top-down and cross-sectional views of a conventional CMOS pixel cell 100, when incident light 187 strikes the surface of a photodiode photosensor 120, electron/hole pairs are generated in the p-n junction of the photodiode photosensor 120 (represented at the boundary of n-type accumulation region 122 and p+type surface layer 123). The generated electrons (photo-charges) are collected in the n-type accumulation region 122 of the photosensor 120. The photo-charges move from the initial charge accumulation region 122 to a floating diffusion region 110 via a transfer transistor 106. The charge at the floating diffusion region 110 is typically converted to a pixel output voltage by a source follower transistor 108 and subsequently output on a column output line 111 via a row select transistor 109.
Conventional CMOS imager designs, such as the one shown in FIG. 1 for pixel cell 100, provide approximately a fifty percent fill factor, meaning only half of the cell 100 is dedicated to converting light to charge carriers. As shown, only a small portion of the cell 100 comprises a photosensor 120 (e.g., photodiode). The remainder of the pixel cell 100 includes isolation regions 102, shown as STI regions in a substrate 101, the floating diffusion region 110 coupled to a transfer gate 106′ of the transfer transistor 106, and source/drain regions 115 for reset 107, source follower 108, and row select 109 transistors having respective gates 107′, 108′, and 109′. In the conventional pixel cell 100 layout, each of the reset, source follower and row select transistor gates 107′, 108′, 109′ are aligned consecutively, sharing source/drain regions 115 and requiring significant surface area for each pixel cell 100. As scaling of pixels continues to decrease the pixel's 100 total area, it becomes increasingly important to create high sensitivity photosensors that utilize a minimum amount of surface area, or to find more efficient pixel cell layouts to minimize the area required by non-photosensitive components of the pixel cell in order to maintain relatively large areas for the photosensors.
A CMOS imager circuit is often associated with a color filter, such as a Bayer color filter for discerning varying wavelengths of light. Referring now to FIG. 3A, a color filter 30 is typically a polymer-based film sensitive to different wavelengths in the visible spectrum. Each pixel of a CMOS imager is covered with a color filter, typically a red, blue, or green filter. These color filters together comprise a color filter array (“CFA”) arranged in a specific pattern. This pattern, or sequence, of filters can vary, but the “Bayer” CFA 50 pattern, has been widely adopted due to the human eye's sensitivity to green light. A typical Bayer CFA 50 pattern consists of rows of alternating red (R) and green (G) color filters and alternating blue (B) and green color filters as shown in FIG. 3A. Each color filter 30 in a Bayer CFA 50 corresponds to one pixel in an underlying CMOS imager. However, as pixel cell size decreases, the imager's sensitivity to blue light also decreases; thus, the conventional Bayer CFA 50 may not allow an underlying pixel to accurately detect blue light.
There is, therefore, a need and desire for a pixel cell with improved fill factor and a color filter array for use with the pixel cells. Additionally, there is a need and desire for a pixel cell arrangement in which the size of individual pixel cells may be customized.